The damascene and dual damascene processes for forming interconnect structures such as metal lines, vias and other interconnects in integrated circuits are well known to those skilled in the art. These processes typically require the formation of a metal seed layer over a wafer surface (including on the side walls and floor of any trench structures produced at locations where metal interconnect structures are desired). The seed layer is required in order to provide a low-resistance electrical path which supports a subsequent uniform metal electroplating over the wafer surface to be accomplished. The metal electroplating process fills the lined trench structures and defines the resulting interconnect structures of a metallization layer for the integrated circuit.
Reference is now made to FIGS. 1A-1F (not drawn to scale) which illustrate process steps for forming a metal interconnect structure of an integrated circuit in accordance with the prior art. The known damascene process may generally be described as follows: As shown in FIG. 1A, a wafer 10 is formed which comprises a semiconductor substrate 12 including integrated circuit devices formed in and/or on the substrate (not shown), a pre-metal dielectric (PMD) layer 14 overlying the substrate, and a plurality of electrical contact members 16, such as tungsten plugs or the like, extending through the PMD layer to reach the integrated circuit devices. The pre-metal dielectric (PMD) layer 14 is planarized using, for example, chemical mechanical polishing (CMP) to provide a flat surface for supporting metallization layers of the integrated circuit device. Next, a low-k intermetal dielectric layer 18 is provided over the PMD layer 14 (FIG. 1B), the dielectric layer 18 for example being formed of a multilayer structure including a low-k layer and one or mask layers (for example including a TEOS mask and titanium nitride mask). This low-k intermetal dielectric layer 18 is also planarized. A trench 20 is then formed extending into and perhaps through the low-k intermetal dielectric layer 18 (FIG. 1C). The trench 20 is provided at a location where an interconnect structure is to be located, and in a preferred implementation will have a depth sufficient to expose the top surface of the underlying electrical contact member 16. A blanket formation of a diffusion barrier layer 22 is then made (FIG. 1D) on the wafer (including over the top of the low-k intermetal dielectric layer 18 and on the side walls and floor within the trench 20). This diffusion barrier layer 22 serves to block the migration of subsequently deposited metal atoms for the interconnect structure into the low-k intermetal dielectric layer, as well as block the diffusion in the opposite direction of contaminants from the low-k intermetal dielectric layer to the interconnect structure. Next, a metal seed layer 24 is formed on the wafer (FIG. 1E) using any suitable deposition process such as sputtering over the diffusion barrier layer 22. This seed layer 24 covers the diffusion barrier layer 22 on the top surface of the low-k intermetal dielectric layer 18 as well as the side walls and floor of the trench 20. Optionally, a metal liner layer (not shown) may be deposited between the diffusion barrier layer 22 and the metal seed layer 24. Further optionally, a seed layer etchback (not shown) may be performed to reduce metal overhang at the top corners of the trench 20. An electroplating process is then performed on the wafer to cause the remaining open portion of the trench 20 to be filled with metal 26 (FIG. 1F). Electroplated metal is also produced above the top of the wafer. Chemical mechanical polishing (CMP) is then performed to remove the excess and unwanted portions of the diffusion barrier layer 22, the metal seed layer 24 and the electroplated metal 26 which are located outside of the trench (FIG. 1G). The polishing operation further provides a flat top surface for the wafer that is ready for further integrated circuit processing. As part of that further processing, a dielectric cap layer 28 may be deposited on the flat top surface to protect the low-k intermetal dielectric layer and the metal layers and materials of the formed metal lines and interconnects (FIG. 1H).
The processes of FIGS. 1B-1H may then be repeated, as needed, to form additional metallization layers for the integrated circuit device. In this context, it will be understood that the underlying electrical contact member 16 could thus comprise the metal filled trench of an underlying metallization layer and the dielectric cap layer 28 could thus comprise one of the layers within the low-k intermetal dielectric layer 18.
The metal selected for the metal seed layer 24 and the electroplated metal 26 is typically copper. The diffusion barrier layer 22 is typically tantalum nitride. It will, of course, be understood that other materials could instead be chosen.
It is known in the art to add a dopant material to the copper sputtering target used in the deposition of the metal seed layer 24 (i.e., the sputtering target is formed of copper alloyed with another material). For example, the dopant may comprise manganese (Mn) or aluminum (Al). The added dopant material will typically be substantially uniformly distributed throughout the deposited copper seed layer 24. In other words, and with reference to concentration line 302 in FIG. 3, there will exist a relatively uniform doping concentration as a function of trench depth for the metal seed layer 24.
During the high temperature process used to form the dielectric cap layer 28, as well as during further other thermal cycles and processing operations associated with completing fabrication of the integrated circuit (such as with the addition of further metallization layers), those skilled in the art understand that the added dopant species may migrate from the copper seed layer 24 and diffuse through the electroplated copper metal 26 fill to form a self-aligned metal cap located at the interface 30 between the dielectric cap layer 28 and the electroplated copper metal 26 which fills the trench 20. It is desirable for a high percentage of the added dopant species to migrate from the seed layer 24 to the interface 30 between the dielectric cap layer 28 and the electroplated metal 26 which fills the trench 20 because this interface tends to be the initiation area of copper electromigration which can lead to circuit failure. However, a not insignificant fraction of the added dopant species, especially the dopant species located in the copper seed layer 24 near the bottom of the trench 20, have difficulty in successfully migrating to the interface 30 area for the self-aligned metal cap. The reasons for this failure include: the traveling distance is too long, the migration time is too short, and dopant species trapping locations may exist within the electroplated metal 26 fill near the bottom of the trench 20. The trapped or unsuccessfully migrated doping species can significantly affect subsequent copper grain growth and produce an unacceptable increase in copper line resistance.
Thus, it is desirable to segregate the doping species toward the interface 30. The failure to segregate can result in shorter electromigration life time and increased metal line resistance. The retention of doping species in the seed layer or fill away from the interface affects copper grain growth resulting in copper microstructures with high electrical resistance.
As semiconductor processing techniques move to finer geometries, the interface 30 between the electroplated copper metal 26 fill and the dielectric cap layer 28 presents a significant challenge to ensuring satisfactory reliability performance. There would be an advantage to having a seed layer formation process which supports better segregation of the dopant species from the seed layer 24 to the interface 30 in order to form a self-aligned metal cap where there would otherwise not exist a sufficient barrier or adhesion layer.